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SX1210
ADVANCED COMMUNICATIONS & SENSING
When the FIFO is full, Fifofull IRQ source is asserted to alert the uC, that at that time, the FIFO can still be unfilled
without data loss. If the FIFO is not unfilled, once the SR is also full (i.e. 8 bits periods later) Fifo_overrun_clr is
asserted and SR’s content is lost.
Figure 31 illustrates an Rx processing with a 16 bytes FIFO size and Fifo_fill_method=0. Please note that in the
illustrative example of section 5.4.5, the uC does not retrieve any byte from the FIFO through SPI Data, causing
overrun.
Data Rx
(to SR)
“noisy” data
Preamble
Sync
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11 b12 b13 b14 b15 b16
Start condition
(Cf. Fifo_fill_method)
/Fifoempty
Fifofull
Fifo_overrun_clr
Write_byte
15
FIFO
0
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
Figure 31: Rx Processing in Buffered Mode (FIFO size=16, Fifo_fill_method=0)
5.4.3. Interrupt Signals Mapping
The tables below describe the interrupts available in Buffered mode.
Rx_stby_irq_x
00 (d)
-
Rx
-
Stby
IRQ_0
IRQ_1
01
10
11
00 (d)
01
10
11
Write_byte
/Fifoempty
Sync
-
Fifofull
RSSI
Fifo_threshold
-
/Fifoempty
-
-
Fifofull
-
Fifo_threshold
Table 17: Interrupt Mapping in Buffered Rx and Stby Modes
Rev 2– Sept 8 , 2008
th
Page 39 of 73
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